A model computer simulation as an epistemic game.

Sherry, L. (1995). A model computer simulation as an epistemic game. ACM SIGCSE Bulletin, 27 (2), 59-64.

Copyright © Association for Computing Machinery.

In the 1980's, psychologists began to investigate the construction of 
knowledge through general purpose strategies.  They found that the 
art and science of computer programming was often aided by the use 
of visualizations, simulations, and interactive systems.  Ackerman 
and Stelovsky (1986) define such an interactive system as a 
supporting tool which helps students with the transition process 
between their intuitive reality or mental models, and the external 
reality of data processing with accurate specifications.

Recently, researchers such as Mayerhofer and deLucena (1992), Naps 
(1994), Styer (1994), and many others have devised animated 
simulators for data structures, algorithms, and computer 
architecture. Sophisticated, dynamic structures such as these allow 
students to

	* visualize the flow of data through the CPU and its associated 
	I/O devices,

	* see how the fetch-execute cycle is executed,

	* step through sorting, searching, and hashing routines and 
	other algorithms, and/or

	* develop a visual conception of computer processing.

These simulators, described in SIGCSE Bulletin and elsewhere, were 
designed with computer science majors in mind, and have a proven 
success record.  However, less effort has been expended for novice 
students at the community college level who are taking CS101, many 
of whom may not take CS courses beyond the beginning level. 

Typically, CS majors study a high-level language such as Pascal, 
followed by data structures, followed by an assembly language.  Only 
then does the student begin to find out what is going on at the 
processor level during program execution.  For perhaps the entire 
first year of study, the role of the processor is largely a mystery.

This article presents a model computer, titled MPC1, specifically 
designed for the beginning student.  (See Johnson, 1995, for a full 
description of MPC1.)  Though limited in scope, it allows students to 
concentrate on basic principles rather than having to worry about 
the many physical and logical details of a more powerful computer.  
It has been used successfully for seven semesters at Massachusetts 
Bay Community College, three semesters at the University of South 
Florida, and will soon be introduced in a model classroom at 
Arapahoe Community College which deals with epistemic games for 
knowledge construction (see Trigg and Sherry, 1994).

We will start with the theoretical basis on which model computers, 
animated algorithms, and associated simulations are developed:  the 
concept of epistemic forms and epistemic games.  Then we will show 
how MPC1, an epistemic game based on a model processor (see 
Figure 1),  enables beginners to gain a basic understanding of how 
computers function.


Figure 1 shows a functional block diagram of a model computer.  Its
component parts are:

RAM (64 RAM addresses numbered 0 through 63, in an 8 x 8 matrix)
Monitor (output)
Keyboard (input)
Disk (storage)
Three registers:  accumulator, instruction register, program counter
Message Box

Figure 1.  A Model Processor 

MPC1:  an epistemic game  

MPC1, a model processor, is an example of a form-and-function 
analysis game.  With it, students begin to comprehend the role, 
function, structure, and mechanism of a real computer: 

	* role (the part played by each component, such as RAM, 
	registers, and I/O buffers

	* function (the goal that each component accomplishes)

	* structure (architecture), and

	* mechanism (the process by which the structure accomplishes 
	the function).

(See Weld, 1983, for a detailed analysis concerning how these four 
aspects explain the workings of a physical device.)

MPC1 resides on a single DSDD DOS disc, and runs on any stripped-
down PC.  It is roughly equivalent to a programmable calculator that 
is limited to integer arithmetic.  Nonetheless, it contains many of the 
essential components of a real processor:  input and output buffers, 
64 RAM cells, three registers (accumulator, instruction register, and 
program counter), and a message box.

The MPC1 software displays the movement of data through the 
processor during execution of a machine code program.  Students can 
watch the program counter increment as an instruction is read into 
the instruction register.  They can see the data move from the input 
buffer to RAM, to and from the accumulator, with each fetch-execute 
cycle, and finally arrive at the output buffer.  As they become 
familiar with MPC1's architecture, students learn a set of ten 
rudimentary machine code instructions.

Table 1 lists the ten machine instructions, represented by numeric 
operation codes, that can be understood and executed by MPC1.


Table 1 shows the ten numeric MPC1 opcodes and their meanings:

0	[STOP program execution.]
1	[LOAD the accumulator (ACC) with data from a specified 
	memory (RAM) cell.]
2	[STORE the current contents of the ACC at a specified RAM cell.]
3	[ADD the data at a specified RAM cell to the current
	contents of the ACC.]
4	[SUBTRACT the data at a specified RAM cell from the current
	contents of the ACC.]
5	[INPUT data at the keyboard and place it at a specified RAM 
6	[PRINT the data found at a specified RAM cell.]
7	[If the current ACC value is NEGATIVE, reset the program 
	counter (PCR) to a specified address.]
8	[If the current ACC value is 0, reset the PCR to a specified 
9	[Reset the PCR to a specified address, without regard to the
	current ACC value.]

Table 1.  The MPC1 Machine Instruction Set

MPC1's processor can also read and interpret the two alphabetic 
characters, "D" (for DATA) and "I" (for INSTRUCTION).

Each complete MPC1 instruction consists of two parts:  an opcode and 
an operand.  The opcode is one of the ten codes just defined; the 
operand is a memory address.  Students use these instructions to 
write machine language programs which are solutions to integer 
arithmetic problems.  These instructions can be considered as the set 
of moves in an epistemic game.

Program Example 1 is a complete MPC1 machine code program with 
an explanation of each instruction.


Here are the opcodes, operands, and meanings for the seven
machine code instructions in Program Example 1:

5	63	[INPUT a data value; place it in RAM Cell 63]
1	63	[LOAD the data value at RAM Cell 63 into ACC]
3	63	[ADD the data value at RAM Cell 63 to current
		value of ACC]
2	62	[STORE current ACC value at RAM Cell 62]
6	63	[PRINT data value found at RAM Cell 63]
6	62	[PRINT data value found at RAM Cell 62]
0		[STOP program execution]  (The STOP instruction
		does not require an operand.)

Program Example 1.  Doubling an integer 

After an MPC1 program is loaded into RAM, the program runs to 
completion by repeating a fetch-execute cycle until a STOP opcode 
(0) is executed.  With each cycle, the screen display (the epistemic 
form) changes.  

The fetch-execute cycle is a sequence of three events:

1.	Bring (fetch) the instruction stored at the RAM cell named in 
	the program counter (PCR) into the instruction register (IR).

2.	Add 1 to the value in the PCR.  (Point to the next instruction 

3.	Execute the instruction in the IR.

The software enables students to debug flawed programs by 
executing them stepwise.  If we were able to run this MPC1 program, 
and if we were to INPUT a data value of, say, 276, the program 
would double the input value and store the result (552) in its output 

As we step through Program Example 1 to the instruction at RAM 
address 5, we should see the following:


Figure 2 shows a screen capture of the model computer as it executes 
the fifth instruction (Instruction 6 62) of Program Example 1. 

The seven machine code instructions 
(5 63, 1 63, 3 63, 2 62, 6 63, 6 62, 0 0)
are shown in RAM addresses 0 through 6 inclusive.  At the moment 
instruction 6 62 is executing, the values shown on the screen are:

Input			(276)
Output			(276, 552)
Accumulator		(552)
Instruction Register	(6 62)
Program Counter		(6)
RAM address 62		(552)
RAM address 63		(276)

Figure 2.  The Fetch-Execute cycle for the instruction 6 62

1.	Instruction at RAM Cell 5 is fetched to IR.

2.	PCR is incremented from 5 to 6.

3.	Data value from RAM Cell 62 is OUTPUT.

Ancillary Materials  

There is a manual which accompanies the software.  It is consists of 
four parts:

1.	a detailed description of the MPC1 processor and its instruction 

2.	machine code programming and algorithm development,

3.	the use of mnemonics and the MPC1 assembly language, and

4.	number systems as they apply to computers.

Numerous examples are given, with a detailed breakdown of the 
solution process.  There are also problem sets and a test at the end of 
each section.

MPC1 has been used as an enhancement to, and as the beginning 
module of, a course in Pascal I (CS101).  It has also been used as a 
computer-based tool in a master's degree level hardware course for 
K-12 media specialists, and as an example of an epistemic game in a 
professional development program to introduce teachers to the 
principles of constructivism.  It is available as an ancillary 
publication from West Publishing Company.


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programming:  from experiments to requirements for an interactive 
system.  In S.K. Chang (Ed.), _Visualization in Programming:  Fifth 
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Collins, A., & Ferguson, W.  Epistemic forms and epistemic games: 
Structures and strategies to guide inquiry.  _Educational Psychologist, 
28_(1), 25-42.

Johnson, R.E.  (1995).  _A Model Computer_.  Minneapolis:  West 
Publishing Company.

Mayerhofer, M.A., & de Lucena, C.J.P., (1992).  Design of an algorithm 
simulation and animation environment.  _SIGCSE Bulletin, 24_(2),  7-

Naps, T.L.  (1994).  An object-oriented approach to algorithm 
visualization - easy, extensible, and dynamic.  _SIGCSE Bulletin, 
26_(1), 46-50.

Styer, E.  (1994).  On the design and use of a simulator for teaching 
computer architecture.  _SIGCSE Bulletin, 26_(3),  45-50.

Trigg, M., & Sherry, L.  (1994).  _Creating and playing epistemic 
games_. Unpublished manuscript, University of Colorado at Denver.

Weld, D.S. (1983).  _Explaining complex engineered devices_ (Tech. 
Rep. No. 5489).  Cambridge, MA:  Bolt Beranek and Newman.